SC418
8
V
OUT
V
IN
+
CIN
Q2
+
D2
R
ILIM
C
BST
Q1
L
PGND
DL
ILIM
LX
DH
BST
C
OUT
Figure 9 Valley Current Limit
Setting the valley current limit to 0A results in a peak
inductor current of 0A plus peak ripple current. In this
situation the average current through the inductor is 0A
plus one-half the peak-to-peak ripple current.
The R
ILIM
value is calculated by the next equation.
A
10
I
R
R
LIM
DSON
ILIM
The internal 0糀 current source is temperature compen-
sated at 400ppm in order to provide tracking with the
RDS
ON
.
Note that MOSFET RDS
(ON)
increases significantly if the
VDDP voltage is 3.3V compared to 5.0V. When selecting
the R
ILIM
value, use the RDS
(ON)
value that corresponds to
the VDDP voltage used in the application.
Soft-Start of PWM Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB compara-
tor. The voltage ramp is generated using an internal
charge pump which drives the reference from zero to
500mV in .2mV increments, using an internal 500kHz
oscillator. When the ramp voltage reaches 500mV, the
ramp is ignored and the FB comparator switches over to a
fixed 500mV threshold. During soft-start the output
voltage tracks the internal ramp, which limits the start-up
inrush current and provides a controlled soft-start profile.
Typical soft-start ramp time is 850約.
During soft-start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero,
regardless of the psave setting. This prevents negative
inductor current, allowing the device to start into a pre-
biased output.
Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the
FB pin is 0% below the nominal voltage, PGOOD is pulled
low. It remains low until the FB voltage returns above -8%
of nominal. During start-up PGOOD is held low and will
not be allowed to transition high until the PGOOD start-
up delay fime has passed and soft-start is completed
(when V
FB
reaches 500mV). The delay time starting from
EN going high is typically 2ms for VDDA = 5V and ms for
VDDA = 3.3V.
PGOOD will transition low if the FB voltage exceeds +20%
of nominal (600mV), which is also the over-voltage shut-
down threshold. PGOOD also pulls low if the EN pin is low
when VDDA is present.
Output Over-Voltage Protection
OVP (Over-voltage protection) becomes active as soon as
the device is enabled. The OVP threshold is set at 500mV
+ 20% (600mV). When V
FB
exceeds the OVP threshold, DL
latches high and the low-side MOSFET is turned on. DL
remains high and the controller remains off until the EN
input is toggled or VDDA is cycled. There is a 5約 delay
built into the OVP detector to prevent false transitions.
PGOOD is also low after an OVP event.
Output Under-Voltage Protection
When V
FB
falls 25% below its nominal voltage (falls to
375mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tri-
state the MOSFETs. The controller stays off until EN is
toggled or VDDA is cycled.
VDDA UVLO and POR
The VDDA Under-Voltage Lock-Out (UVLO) circuitry inhib-
its switching and tri-states the DH/DL drivers until VDDA
rises above 2.9V. When VDDA exceeds 2.9V, an internal
POR (Power-On Reset) resets the fault latch and the soft-
start counter and then the SC48 begins the soft-start
Applications Information (continued)
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